(1) Field of the Invention
The present invention relates to the fabrication methods used for semiconductor devices, and more specifically to an optimized process for creating the interconnecting contact stud, between the active device region and the overlying metallization.
(2) Description of Prior Art
The trend in the semiconductor industry has been to manufacture silicon chips, featuring increasing device density and performance, while still however reducing, or maintaining costs. This has been accomplished by the ability of the semiconductor industry to continually reduce the size of device features, thus enabling greater densities to be achieved. The decreasing device dimensions have also benefitted performance objectives, in terms of allowing reduced capacitances and resistances to be realized.
The ability of the semiconductor industry to reduce critical device dimensions, to the sub-micron range, has largely been attributed to advances in several key semiconductor fabrication disciplines. For example achievements in photolithography, via the use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed micro-miniaturazation to proceed. In addition the rapid development of anisotropic dry etching procedures have allowed the sub-micron images, in masking photoresist, to be successfully transferred to underlying materials used in silicon chip fabrication processes. Other semiconductor fabrication disciplines, such as ion implantation as well as low pressure chemical vapor deposition, (LPCVD), have also been major contributors to the attainment of micro-miniaturazation.
Although these now achievable smaller devices can easily be manufactured, directly reducing cost and improving performance, specific vulnerabilities, in terms of reliability can exist. For example, contact studs, used to interconnect specific silicon device regions to overlying metallizations, can now be formed with diameters in the range of 0.25 to 0.50 micrometers. This reduction in the dimension of a critical device feature, although offering denisty improvements, also can create reliability concerns. For example if an aluminum based metallurgy were used for filling the narrow diameter contacts, the current density in the aluminum filled hole may exceed the capabilities of this material and lead to electromigration failures. In addition the solubility of silicon in aluminum, can lead to deletrious penetration failures, during subsequent processing heat treatments.
A material that can be used to successfully fill these small contact holes, without reliability, or penetration risks, is polysilicon. The current carrying capability of this material, and the ability to reduce the resistance of polysilicon, via conventional doping techniques, suggest this materitel as a excellent candidate for filling narrow contact holes. The problem the industry has been attempting to overcome, when using polysilicon contacts, is the ability to remove the unwanted material from areas other then the contact hole region. For example Bersom, et al, in U.S. Pat. No. 5,196,373, and Nakamo, et al, in U.S. Pat. No. 5,183,781, describe polysilicon contact processes, however without showing exact details needed to execute the fabrication of this structure. In addition Boyd, et al, in U.S. Pat. No. 5,316,998, show a polysilicon contact process using a chemical mechanical polishing procedure, used to remove the unwanted residual material. However this process, in addition to being complex, also can add significant cost to the process. This invention will describe a novel process, used to create a polysilicon contact, to a silicon device region, which is easy to implement, and without exhibiting significant process complexity or cost increases.